IPC LP Calculator:

Three land pattern geometry variations are supplied for each of the device families; maximum land protrusion (Density Level A, Most), median land protrusion (Density Level B, Nominal) and minimum land protrusion (Density Level C, Least).


BGA Surface Mount Nominal

IPC-7351 Surface Mount: IPC-7351B: Least, Nominal, & Most

IPC-7251 Connectors: IPC-7251B: Connectors

IPC-7251 Through Hole: IPC-7251B: THA, THB, THC & THP  (So whats P ??)

And the Starter File, a device specific taster file to encourage us to buy the package..


Notes on TSSOP & TQFP

Updated IPC-7351A Land Pattern Naming Convention - 

"T" (THIN) is defined in the Land Pattern Naming Convention but no where else in the IPC-7351A document. 

"S" (SHRINK) is defined in the Land Pattern Naming Convention but no where else in the IPC-7351A document. 

There was no value for using "S" or "T" characters as they do not define anything of any importance or significance and they are only used for Gull Wing Components (not all components). 

Shrink Example: 
0.625mm pitch was considered "Shrink" in early IPC-SM-782, In the 1990�s 0.5mm pitch was "Shrink", today in 2007 0.4mm pitch is considered �Shrink� and tomorrow 0.3mm pitch will be the new "Shrink" manufacturing benchmark. 

Thin Example: 
1.6mm Height was "Thin" yesterday, now Vern Solberg says 1.2mm Height is "Thin" today and tomorrow 1.0mm Height will be the new "Thin". 

The Thin and Shrink values keep changing with industry advances and "T" & "S" were removed from the IPC-7351A Land Pattern Naming Convention. 

TQFP, SQFP & TSQFP are now simply classified as QFP + Pitch 

TSOP, SSOP, & TSSOP are now simply be classified as SOP + Pitch 

This also removes all the confusion between component manufacturers and world standards. Component manufacturers have different levels of where they define "Shrink" and "Thin".


Example 1: SMD Cap:

I have a part Vishay 293D106X96R3A2TE3 10uF 6.3V Tantalum Cap, molded case Case code A (3216-18) 3.2mm x 1.6mm

Where possible I will use Density Level A (Maximum Land protusion).

In the LPC tool:

- I select library SMM7351B

- Click on categories

- Select Capacitor, polarised, Molded Body

- Click On the little green arrow

Returns a list if search results in which I can see CAPMP3216X180M,  I double click this to view.

By clicking on layers button I can select the silk screen to see the polarity dot.

I can click on the Land Pattern Tab to show the dimensions of the land pattern so I can create a matching pattern in my PCB cad package.


Example 2: PIC32MX 64pin PT (TQFP 10 x 10 x 1 0.5 pitch):

Select library, click categories, double click QFP 0.50 pitch square

Scroll to 64pin, 10 x 10 x 1  etc QFP50P1200X1200X100-64M and double click

Courtyard: 0.05mm thick line.

Zero Orientations for Part Library..:

Chip Res, Cap & Ind (RES, CAP, IND):

  • Pin 1 on left side
  • If polarised: Pin 1 is always +ve (as it seems the positive side is alwsys the marked side?)

Molded Chip Res, Cap & Ind (RESM, CAPM, INDM):

  • Pin 1 on left side
  • If polarised: Pin 1 is always +ve (as it seems the positive side is alwsys the marked side?)

MELF Diodes:

  • Pin 1 on left side
  • Pin 1 is always cathode

Aluminium Electrolytic Caps (CAPAE):

  • Pin 1 (Positive) on left

SOT devices: Pin 1 upper left

TO252 7 TO263 (DPAK): Pin 1 upper left



Trace / Space Size Grid System:

Metric trace width rules are in increments of 0.05mm with one exception 0.125mm (5 mils).
0.25mm = 10 mils
0.20mm = 8 mils
0.15mm = 6 mils
0.125mm = 5 mils
0.10mm = 4 mils
0.075mm = 3 mils
0.05mm = 2 mils

Trace Routing Grid System:
The ultimate metric routing grid is 0.05mm.

Reference Designators and Text Grid System:
0.1mm is the common grid for placing Reference Designators and Text, but 0.05mm is used for tight spaces

Copper Pour and Plane Fill Grid System:
0.1mm is the common grid for Copper Pour outlines and snap grid, but 0.05mm can be used for high-density part placement and trace routing

Mounting Hole Size and Placement Grid System:
All mounting-hole padstacks are in increments of 0.05mm and the placement grid is in 0.05mm increments.





Inch Metric
CAPC, INDC, RESC 0201 0603
CAPC, INDC, RESC 0402 1005
CAPC, INDC, RESC 0603 1608
CAPC, INDC, RESC 0805 2012
CAPC, INDC, RESC 1206 3216
CAPC, INDC, RESC 1210 3225
CAPC, INDC, RESC 1218 3246
CAPC, INDC, RESC 2010 5025
CAPC, INDC, RESC 2512 6332


Standard component rotation:


IPC-7351 Surface Mount Land Pattern Zero Orientation
1) Chip Capacitors, Resistors and Inductors (RES, CAP and IND) – Pin 1 (Positive) on Left
2) Molded Inductors (INDM), Resistors (RESM), Molded Polarized Capacitors (CAPMP) – Pin 1 (Positive) on Left
3) Precision Wire-wound Inductors – Pin 1 (Positive) on Left
4) MELF Diode – Pin 1 (Cathode) on Left
5) SOD Diodes – Pin 1 (Cathode) on Left
6) Aluminum Electrolytic Capacitors – Pin 1 (Positive) on Left
7) SOT Devices (SOT23, SOT23-5, SOT223, SOT89, SOT143, etc.) – Pin 1 Upper Left
8) TO252 & TO263 (DPAK Type) Devices – Pin 1 Upper Left
9) Small Outline Gullwing ICs (SOIC, SOP, TSOP, SSOP, TSSOP) – Pin 1 Upper Left
10) Ceramic Flat Packs (CFP) – Pin 1 Upper Left
11) Small Outline J Lead ICs (SOJ) – Pin 1 Upper Left
12) Quad Flat Pack ICs (PQFP, SQFP) – Pin 1 Upper Left
13) Ceramic Quad Flat Packs (CQFP) – Pin 1 Upper Left
14) Bumper and Plastic Quad Flat Pack ICs (BQFPC, PQFPC Pin 1 Center) – Pin 1 Top Center
15) Plastic Leaded Chip Carriers (PLCC) – Pin 1 Top Center
16) Leadless Chip Carriers (LCC) – Pin 1 Top Center
17) Leadless Chip Carriers (LCCS Pin 1 on Side) – Pin 1 Upper Left
18) Quad Flat No-Lead ICs (QFN) QFNS & QFNRV, QFNRH – Pin 1 Upper Left
19) Ball Grid Arrays (BGA) – Pin A1 Upper Left