Pattern Designer:

Pads are positioned per the center of the pad.

When routing specify trace width, clearance (trace to trace, trace to pad, board) in Route->Route Setup

Use Layers - Via Properties to set autio vias (Note that static vias dont use this setting)

Default minimum trace width & = 0.33mm / 13mil larger where possible (0.4mm / 0.5mm 1mm)

As per Olimex recommendations, start Verification limits at manufacturers tolerances (typically 8mil = 0.2mm) and increase until errors are no longer fixable.  The less you push the tolerances the less manufacturing errors.

Have found that TQFT & SSOP footprints have errors at higher limits as the inter pad gap is small by default..