Peripherals

PMP: Parallel Master Port

There are mainly two ways of interfacing read and write signals:

  • Read and write signals generated on two different pins (most memory devices use this
    type of interface).
  • Read and write signals generated on the same pin with separate enable signals.
    The PMP module in Master mode allows selection of different wait states to suit the electrical characteristics of a particular memory device. The signals used to interface with the memory devices are the address bus, data bus, read signal, write signal, chip select (optional), address latch signal (if required) and byte enable (in case of 16-bit data).

PMD0 to PMD7 (8 data lines):

  • In 8-bit operation, 8-bit data is transmitted/received through these lines.
  • In 16-bit operation, 16-bit data is divided into the Least Significant Byte (LSB) and Most Significant Byte (MSB). First the LSB is transmitted/received through these lines, and then the MSB.

PMBE is a byte enable line, used during 16-bit data operation. It goes active for MSB and inactive for LSB

PMWR can be used as a write line or an enable signal. To interface with a memory device, it should be used as a write line.

PMRD can be used as a read line or a read/write line. To interface with a memory device, it should be used as a read line.